Both analog and digital circuits are often present in system chips. Signals may cross from the digital domain to the analog domain, and vice-versa. Analog signals may be converted to digital for complex digital processing, such as by a Digital Signal Processor (DSP).
Many types of Analog-to-Digital Converters (ADC's) have been used for a wide variety of applications. Flash ADC's compare analog signal voltages to multiple voltage levels in an instant to produce a multi-bit digital word that represents the analog voltage. Successive-approximation ADC's use a series of stages to convert an analog voltage to digital bits. Each stage compares an analog voltage to a reference voltage, producing one digital bit. In sub-ranging ADC's, each stage compares an analog voltage to several voltage levels, so that each stage produces several bits. Succeeding stages generate lower-significant digital bits than do earlier stages in the pipeline.
Algorithmic, re-circulating, or recycling ADC's use a loop to convert an analog voltage. The analog voltage is sampled and compared to produce a most-significant digital bit. Then the digital bit is converted back to analog and subtracted from the analog voltage to produce a residue voltage. The residue voltage is then multiplied by two and looped back to the comparator to generate the next digital bit. Thus the digital bits are generated over multiple cycles in the same comparator stage.
FIG. 1 shows a Successive-Approximation-Register ADC. Successive-Approximation-Register SAR 102 receives a clock CLK and contains a register value that is changed to gradually zero-in on a close approximation of the analog input voltage VIN. For example, the value in SAR 102 may first be 0.5, then 0.25, then 0.375, then 0.312, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, and finally 0.312 when comparing to a VIN of 0.312 volts. SAR 102 outputs the current register value to digital-to-analog converter (DAC) 100, which receives a reference voltage VREF and converts the register value to an analog voltage VA.
The input analog voltage VIN is applied to sample-and-hold circuit 104, which samples and holds the value of VIN. For example, a capacitor can be charged by VIN and then the capacitor isolated from VIN to hold the analog voltage. The sampled input voltage from sample-and-hold circuit 104 is applied to the inverting input of comparator 106. The converted analog voltage VA is applied to the non-inverting input of comparator 106.
Comparator 106 compares the converted analog voltage VA to the sampled input voltage and generates a high output when the converted analog voltage VA is above the sampled VIN, and the register value in SAR 102 is too high. The register value in SAR 102 can then be reduced.
When the converted analog voltage VA is below the sampled input voltage, comparator 106 generates a low output to SAR 102. The register value in SAR 102 is too low. The register value in SAR 102 can then be increased for the next cycle.
The register value from SAR 102 is a binary value of N bits, with D(N−1) being the most-significant-bit (MSB) and D0 being the least-significant-bit (LSB). SAR 102 can first set the MSB D(N−1), then compare the converted analog voltage VA to the input voltage VIN, then adjust the MSB and/or set the next MSB D(N−2) based on the comparison. The set and compare cycle repeats until after N cycles the LSB is set. After the last cycle, the end-of-cycle EOC signal is activated to signal completion. A state machine or other controller can be used with or included inside SAR 102 to control sequencing.
DAC 100 or sample-and-hold circuit 104 may have an array of capacitors. The capacitors have binary-weighted values, such as 1, 2, 4, 8, 16, 32, . . . times a minimum capacitor size. For example, a 6-bit DAC may have an array of capacitors of 1, 2, 4, 8, 16, 32 times a minimum capacitance C. Higher-resolution DAC's such as a 11-bit DAC have much larger capacitor values, such as 2N−1=1024.
FIG. 2 is a graph showing a SAR ADC resolving an input voltage. The register value in SAR 102 is initially set to one-half, or 10000. Comparator 106 determines that the input voltage VIN is less than the converted value from SAR 102, so in the next iteration SAR 102 is set to one-quarter, or 01000. Comparator 106 determines that the input voltage VIN is greater than the converted value from SAR 102, so in the third iteration SAR 102 is set to three-eighths, or 01100. Comparator 106 determines that the input voltage VIN is less than the converted value from SAR 102 in the third iteration, so in the fourth iteration SAR 102 is set to five-sixteenths, or 01010. Now comparator 106 determines that the input voltage VIN is greater than the converted value from SAR 102, so in the fifth iteration SAR 102 is set to 9/32, or 01011. The final comparison is that VIN is above the converted value, so the final result is 01011.
While such capacitor-array DAC's are useful, the large size of the MSB capacitors requires a large amount of charge to be transferred. The minimum capacitor size C can be shrunk to reduce the overall capacitance of the capacitor array and thus reduce the dynamic power requirements. The minimum capacitor size may be restricted by the process technology. For example, a sub-micron process may allow for a 4×4 μm2 minimum physical-size for a metal-to-metal capacitor, which has a capacitance of about 16 fF.
Matching capacitor values in the binary-weighted array is very important for obtaining precise results. Inherent device and impedance mismatches in deep sub-micron processes limit converter resolutions to about 10 bits.
Resolution can be increased through calibration. Before the input voltage is converted to a digital value, a sequence of steps known as calibration can be performed. Calibration measures each capacitor's mismatches by charge sharing with an additional array of capacitors. Capacitors in the additional array are connected and disconnected until a voltage match occurs. A mis-match value is obtained by recording the enable signals for the capacitors once the final voltage match occurs.
The procedure is then repeated for the next capacitor in the main array, and its mis-match value stored. Once the calibration procedure has operated upon all capacitors in the main array, the mis-match values are saved for each of the capacitors as capacitor coefficients. These capacitor coefficients can then program the second array to subtract out the mis-match errors as the analog input voltage VIN is processed. As successively smaller capacitors are evaluated in the main array, their saved capacitor coefficient are applied to the second capacitor array.
ADC error measurements such as Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) can be increased through calibration. Another source of errors is charge injection and clock feed-through caused by switches that connect and disconnect capacitors. Clock feed-through can be different for the main array and for the calibration array of capacitors, thus introducing voltage imbalances and measurement errors. When the switching sequences differ, errors measurement may occur.
What is desired is an ADC with a calibration sub-DAC to measure capacitor mis-match errors. A method of operating a SAR ADC with a calibration sub-DAC is desired to obtain calibration coefficients and improve precision. A calibration procedure for a precision ADC is desired.